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Apply NowDigital Design using VHDL course
Apply Now “Digital Design using VHDL course” Summer 2012 for Communications and Electronics students for Computer students http://www.slideshare.net/StartGroup/intrduction-to-the-course-v3 Join Us on Our Group www.facebook.com/groups/start.group -------------------------- Course Application -------------------------- Please send to [email protected] In E-mail subject write “Digital Design Course” in E-mail body write Full Name University Department and Year (example : ECE 2014 – CSE2013 …) Mobile number ----------------------------------------------------------------------------------- ----------------------------- for more details ----------------------------- visit our website http://startgroup.weebly.com/ Introduction to the course http://www.slideshare.net/StartGroup/intrduction-to-the-course-v3 Facebook Group www.facebook.com/groups/start.group ----------------------------------------------------------------------------------- Course Duration 32 Hours 9 Sessions + Workshop --------------------------- Time For 6th Intake Start of the course 28-6-2012 Thursday at 05:00 pm every week on Thursday and Saturday For 7th Intake will be determined later --------------------------- Attendance Max. 16 per group Graduation Projects groups support --------------------------- Course Costs 400 LE --------------------------- Instructors Eng. Mahmoud Abdellatif Eng. Alaa Salah Shehata Start Group 2011 Founders --------------------------- Course prerequisites Basic Digital /Logic concepts --------------------------- • 50 % Lab ……50 % Illustration • Working Examples, Exercises, Labs, Demos, Quizzes and Assignments are included during the sessions • Mini-projects and Final Project --------------------------- Course overview •To obtain a general appreciation of what VHDL is as a hardware description language, and how it is used in the hardware design process. •To get a comprehensive overview about the VHDL language. •To Create synthesizable models (behavioral coding style) •To Use VHDL component instantiations to create hierarchy (structural coding style) •To understand the role of test-benches in gate level simulation --------------------------- Place اكاديمية نهضة للتدريب 39 عمارات النحاس -- شارع مصطفى النحاس -- مدينة نصر -- امام صيدليات العزبى بجوار معامل المختبر - الدور الاول – مدينه نصر - القاهره https://www.facebook.com/groups/nta4all/ — in Cairo. |