Session One Demo_1 : 2-XOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY AND_GATE IS PORT ( a : in std_logic; b : in std_logic; C : out std_logic ); END ENTITY AND_GATE ;
ARCHITECTURE behave OF AND_GATE IS BEGIN c <= a xor b; --non blocking assignment END behave;
Session Two Lab 01
Architecture rtl of dec is begin process (a) begin Case a is When "00" => f <= “0001”; When "01" => f <= “0010”; When "10" => f <= “0100”; When "11" => f <= “1000”; When others => f <= “ZZZZ”; End case; End process; End rtl ;
Entity d_ff is Port( d, clk, rst : in std_logic; Q,Q_inv : out std_logic); end entity; Architecture behav of d_ff is Signal Q_sig : std_logic;
Begin process(clk, rst) begin If (rst = '1') then Q_sig <= '0'; elsif rising_edge(clk) then
Q_sig <= d; end if; end process;
Q <= Q_sig;
Q_inv <= not Q_sig; end behav;
Session Three Lab 03
Architecture behave of decoder2x4 is Begin F <= "0001" when a = "00" else "0010" when a = "01" else "0100" when a = "10" else “1000" when a = "11" else “ZZZZ"; End behave ;
--------------------------------------------- Architecture behave of decoder2x4 is Begin With a select F <= "0001" when "00", "0010" when "01", “0100" when "10", “1000" when "11", “ZZZZ" when others; End behave ; --------------------------------------------- Architecture behave of encoder4x2 is Begin F <= “00" when a = “1000" else "01" when a = “0100" else "10" when a = “0010" else "11" when a = “0001" else “ZZ"; End behave ;
--------------------------------------------- Architecture behave of encoder4x2 is Begin with A select F <= "00" when “1000", "01" when "0100", "10" when “0010", "11" when “0001", “ZZ" when others; End behave ;
quit -sim vcom register.vhd vsim work.counter add wave sim:/counter/* force -freeze sim:/counter/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/counter/rst 1 0 run force -freeze sim:/counter/rst 0 0 run run run run run